In the art of semiconductor electronics, very large scale integrated (VLSI) circuits typically require power sources of relatively small positive d.c. voltages, in the past typically about +5 volts. As the integrated circuit art progresses, even smaller d.c. voltages are becoming typical. In many situations, however, the only conveniently available power sources are a.c. voltage sources, typically having more than 5 volt peaks. For use by an integrated circuit requiring a power supply of 5 volts d.c., the a.c. voltage can be stepped down by a conventional transformer to about 5 volts peak a.c., and this 5 volt peak a.c. voltage must then be converted to 5 volts d.c. To this end, a semiconductor rectifier circuit can be used, typically a peak detector diode arrangement--that is, a pn junction diode feeding a capacitive load. One basic problem in such an arrangement arises from the forward junction diode voltage drops (about 0.7 volt or more in silicon) encountered in such a conventional peak detector diode arrangement. Thus, for an input a.c. voltage of peak E=5.0 volts, the output voltage is less than about 4.3 volts, that is, in the range of about 0.7 volt to 1.0 volt or more below E for semiconductor junctions in silicon. As a consequence, undesirably large power losses result.
For alleviating this problem, one approach of prior art, as illustrated in FIG. 1, is taught in "Improving Power Supply Efficiency with MOSFET Synchronous Rectifiers," by R. S. Kagan et al, Proceedings of Powercon 9, Ninth International Solid-State Power Electronics Conference (July 1982), Session D, Paper D-4, pp. 1-5, at p. 4, Sections 6.1-6.3. Briefly, in that approach as shown in FIG. 1, a full-wave rectifier circuit arrangement 10 includes a pair of power MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) 101 and 102, each hereinafter called a "power FET." Secondary transformer windings 111 and 121, energized by primary transistor windings 11, deliver a.c. input to the power FETs. Each power FET is inherently connected in parallel with its inherent unidirectional current inhibiting diode characteristic (indicated by dotted lines in FIG. 1), and each such power FET is connected in a conventional diode peak rectifier arrangement with respect to the input supplied to secondary transformer windings 111 and 121, respectively, and feeds output power to a resistive load (not shown) connected in parallel with a capacitive load C.sub.L. To reduce the forward diode voltage drop, each power FET is turned on periodically by means of a sample (feed-forward) of the a.c. input delivered to the gate terminal of the FET. More specifically, the gate electrode of each power FET is fed input by an auxiliary a.c. voltage developed by auxiliary secondary transformer windings 112 and 122, respectively. Thereby one of the power FETs (101) is turned on, and is maintained on, only in a time-neighborhood of the peak of the a.c. input cycle, i.e., only when the a.c. input is at or near its peak (maximum) value; and the other of the power FETs (102) is turned on, and is maintained on, only in the neighborhood of each trough (minimum) of the a.c. cycle. In this way, the output voltage E.sub.OUTPUT developed across an output load having a capacitive loading C.sub.L desirably does not suffer from a full forward diode voltage drop. However, the gate-to-source voltage of the power FET thus varies as (E.sub.1 -E.sub.2) sin (2.pi.ft), where E.sub.1 and E.sub.2 are the peak voltages, respectively, delivered by the auxiliary transformer windings to the gate and source of the power FET, where f is the frequency of the a.c. input, and t is the time. Therefore, each turning on (and temporary) remaining on) of the power FET at and near the peak of each a.c. cycle, when sin (2.pi.ft) approaches its maximum value of unity, is not a sudden process, but is characterized by the relatively smooth and long transition characteristic of (E.sub.1 -E.sub.2) sin ( 2.pi.ft) when sin (2.pi.ft) is approximately equal to .+-.1. Accordingly, undesirably large amounts of energy are lost in the power FET during each a.c. cycle because of relatively large currents flowing therethrough (during the slow transitions) during time intervals when sin (2.pi.ft) is very nearly equal to .+-.1, i.e., intervals when the voltage drop across the FET is not negligible.
Another approach is taught by S. Waaben, one of the inventors herein, in a paper entitled "FET Switching Devices for Powering of Telecommunications Circuits," published in Proceedings of Intelec 81, pp. 250-252, Third International Telecommunications Energy Conference (May 1981). In that approach, a photoemitter (light-emitting diode) controlled the on-off condition of a photodetector which, in turn, controlled the on-off condition of a "power FET" arranged in a conventional peak rectifier arrangement, i.e., an arrangement of the power FET (with its inherent unidirectional current inhibiting diode characteristic) feeding a capacitive output load. Specifically, the timing of the on-off condition of the photoemitter was arranged to control the timing of the power FET in a manner similar to the timing discussed above in connection with FIG. 1. Rectifier operation resulted in which voltage and power losses--otherwise caused by semiconductor diode junction forward voltage drops and by slow on-off transitions of the power FET--could be reduced substantially. However, the use of the optical control technology (photoemitters and photodetectors) means that the circuit was a three-terminal device including ground (one optical terminal and two electronic terminals) and entails obvious disadvantages in complexity and cost.
Therefore, it would be desirable to have a rectifier circuit arrangement which mitigates these problems of prior art.